This application claims benefit of Japanese Patent Application No. 2000-289961 filed on Sep. 25, 2000, the contents of which are incorporated by the reference.
The present invention relates to data transmission system and method effectively applicable to data transmission system such as an electronic camera, in which data is transmitted from a certain processing block for performing data processing or a buffer to the next stage processing block or buffer.
Data transmission between two processing blocks has heretofore been performed as follows. As shown in FIG. 12, data is to be transmitted from a first block to a second block, the first block notifies a data transmission request to the second block, then obtains a permission from the second block, and then transmits the data. However, when it becomes impossible to transmit data to the second block, for instance when the data reception capability of the second block becomes zero so that data can no longer be written therein, the data to be transmitted to the second block has to be held at the first block side output side terminal. This means that a data holding memory has to be provided at the first block output terminal. When the first block sends out a data transmission request to the second block afresh and responsive to receipt of a permission from the second block, the remaining data (or all the data) is transmitted from the first block.
As shown, in the prior art, even when the succeeding stage processing block is in a state of permitting the writing of data, a desired quantity of data may not always be transmitted, and for this reason a memory for holding data to be transmitted should be provided at the output terminal of the preceding stage processing block. In addition, when the succeeding stage processing block becomes incapable of writing data during data transmission, a waiting time is brought about after the notification of a new data transmission request till the permission of writing data is obtained. A time lag is therefore caused, which is undesired for efficient data transmission.
As shown above, the prior art data transmission has the problems that a memory having a data capacity corresponding to the data to be transmitted should be provided on the preceding processing block output side and that it is impossible to obtain efficient data transmission.